High-speed Design Of High-resolution Dacs

Tez (Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2009Thesis (PhD) -- İstanbul Technical University, Institute of Science and Technology, 2009Bu çalışmada, yüksek çözünürlüklü akım yönlendirmeli sayısal-analog dönüştürücülerin (SAD) hızlı tasarımını sağlayan yöntemler incelenmekte ve yeni yaklaşımlar önerilmektedir. Veri dönüştürücüler analog ve sayısal dünyalar arasında bir köprü oluşturdukları için hızlı ve verimli bir şekilde gerçekleştirilmeleri yüksek derecede arzu edilmektedir. Yüksek hızlı (birkaç 100MHz) ve yüksek çözünürlüklü (10 bitten fazla) SAD için artan rağbet, akım yönlendirmeli SADların kullanımını zorunlu kılmaktadır. Yüksek performanslı akım yönlendirmeli SADların tasarımında ve gerçekleştirmesinde kesimleme (segmentation) yöntemi kullanılmaktadır. Bu yöntem, yüksek hız ve yüksek çözünürlük gerektiren uygulamaların çoğunda avantajlı olmasına rağmen uzun süreli tasarım zamanı, karmaşıklık ve yüksek maliyet yüzünden değer kaybetmektedir. Böylece, bazı uygulamalar için zaman ve maliyet açısından bu yöntemin kullanılması hızlı ve verimli olmayabilir. Bu problemlerin üstesinden gelmek için yüksek çözünürlüklü SADların yüksek hızlı tasarımını sağlayan hızlı ve verimli yöntemler dikkate alınmaktadır. Uygun bir tasarım yöntemi ve yeni bir yapı önerilmektedir. Akım yönlendirmeli SADlar gibi karmaşık karma yapılı sistemlerin tasarımı için davranışsal modelin oluşturulması zorunlu olmaktadır. Bu amaçla gerçekleştirilen modellerin çoğu sistemin davranışı hakkında istenilen eksiksiz manzarayı vermemektedir. Bu yüzden, transistor seviyesindeki tasarıma geçmeden önce, tasarımı hızlandırabilen ve sistemin davranışını doğru bir şekilde yansıtabilen modeller geliştirilmektedir. SIMULINK® kullanılarak bir davranışsal model kurulmakta ve modelin performansı benzetimlerle sınanmaktadır. Sonuç olarak, uygulanan yöntemin verimliliğini ve davranışsal modelin doğruluğunu sınamak için 0.35µm CMOS proses teknolojisi için tasarlanan bir 12 bitlik melez akım yönlendirmeli SAD kullanılmaktadır. Yapı bloklarında yapılan iyileştirmeler ve kullanılan farklı yöntemler, gerçekleştirilen SAD’ın serimindeki ilgili kısımlarda yer almaktadırlar. CADENCE Geleneksel Tümleşik Devre Tasarım Araçları kullanılarak serim sonrası benzetimleri yapılmakta ve SAD’ın performans karakteristikleri incelenmektedir.In this thesis, different problems related to the design speed-up of high-resolution current-steering digital-to-analog converters (DAC) are addressed and novel solutions are proposed. Since data converters form the bridge between the analog and digital world their efficient implementation is highly desirable. The increase in demand for high-speed (several 100MHz) and high-resolution (higher than 10-bit) DAC, forces the use of current-steering DACs. Segmentation method is used for the design and the implementation of high performance current-steering DACs. Although this methodology is advantageous in most of the applications requiring high-speed and high-resolution, it suffers from the prolonged design time, complexity and high cost. Thus, the use of this methodology for some applications is not efficient concerning the time and the cost. To overcome these problems efficient methodologies for the high-speed design of high-resolution DACs are considered. A proper design methodology and a novel architecture are introduced. Behavioral modeling is necessary for the design of complex mixed-mode systems like current-steering DACs. Most of the models constructed can not give a complete view of the system’s behavior. For this reason, models that speed up the design and reflect accurately the behavior of the system prior to transistor level implementation are developed. A SIMULINK® based behavioral model is developed and verified through simulations. To conclude, the efficiency of the applied methodology and the accuracy of the behavioral model are validated through the implementation of a 12-bit hybrid current-steering DAC in a 0.35µm CMOS process technology. The improvements in the building blocks and the different approaches used are reflected in the respective parts of the layout of the implemented DAC. Post-layout simulations are obtained using CADENCE Custom IC Design Tools and the performance metrics of the DAC are investigated.DoktoraPh

New design approach for high-resolution current-steering DACs

Günümüzde Sayısal-Analog Dönüştürücüler (SAD) birçok elektronik sistemlerin kilit elemanları olmaktadır. Veri dönüştürücüler analog ve sayısal dünyalar arasında bir köprü oluşturdukları için hızlı ve verimli bir şekilde gerçekleştirilmeleri yüksek derecede arzu edilmektedir. Özellikle haberleşme uygulamalarında yüksek hızlı (birkaç 100 MHz) ve yüksek çözünürlüklü (10-bitten fazla) SADlar için artan rağbet, akım yönlendirmeli SAD’ların kullanımını mecbur kılmaktadır. Yayınların çoğunda yüksek performanslı akım yönlendirmeli SAD’ların tasarımında ve gerçekleştirmesinde kesimleme (segmentation) yöntemi kullanılmaktadır. Bu yöntem, yüksek hız ve yüksek çözünürlük gerektiren uygulamaların çoğunda avantajlı olmasına rağmen uzun süren tasarım zamanı, karmaşıklık ve yüksek maliyet yüzünden değer kaybetmektedir. Böylece, bazı uygulamalar için zaman ve maliyet açısından bu yöntemin kullanılması hızlı ve verimli olmayabilir. Bu problemlerin üstesinden gelmek için yüksek çözünürlüklü SADların hızlı tasarımını sağlayan verimli yöntemler dikkate alınmaktadır. Akım yönlendirmeli SADlar gibi karmaşık karma yapılı sistemlerin tasarımı için davranışsal modelin oluşturulması zorunlu olmaktadır. Bu amaçla yapılan modellerin çoğu (matematiksel veya devre tabanlı), sistemin davranışı hakkında istenilen eksiksiz manzarayı vermemektedirler. Bu yüzden tasarımı hızlandırabilen ve sistemin davranışını doğru bir şekilde yansıtabilen modeller geliştirilmektedir. Sonuç olarak uygulanan yöntemin verimliliğini ve davranışsal modelin doğruluğunu sınamak için AMS 0.35µm CMOS proses teknolojisi için tasarlanan bir 12 bitlik melez akım yönlendirmeli SAD kullanılmaktadır. Yapılan iyileştirmeler ve kullanılan farklı yöntemler gerçekleştirilen SAD’ın serimindeki ilgili kısımlarda yer almaktadırlar. CADENCE Geleneksel Tümleşik Devre Tasarım Araçları kullanılarak serim sonrası benzetimleri yapılmaktadır ve SAD’ın performans karakteristikleri incelenmektedir. Anahtar Kelimeler: Sayısal-analog dönüştürücü, akım yönlendirmeli, davranışsal model, melez SAD.Nowadays DACs have become key elements in many electronic systems. In order to interface electronic systems with the real world, digital signals have to be translated into physical signals, which require a conversion into analog signals that is performed by DACs. Since data converters form the bridge between the analog and digital world their efficient implementation is highly desirable. The increase in demand for high speed (several 100 MHz) and high resolution (higher than 10-bit) DACs, especially in communication applications forces the use of current-steering based DACs. The current-steering DACs are widely used, since they satisfy the requirements of high-speed and high-resolution necessary in communication applications. However, due to their numerous features and wide range of application uses, it is very difficult to define and to follow a single way in which current-steering DACs can be specified and designed. A similar systematic design methodology can be considered during design flow of a predetermined current-steering DAC architecture. Such a methodology is concerned with the entire mixed signal system and requires a top-down design flow starting with DAC's specifications, architectural decisions, cell-level circuit decisions and ending with DAC layout issues both for digital and analog parts of the system.Most publications made use of the segmentation method for the design and the implementation of high performance current-steering DACs. Although this methodology is advantageous in most of the applications requiring high-speed and high-resolution, it suffers from the prolonged design time, complexity and high cost. Thus, the use of this methodology for some applications is not efficient concerning the time and the cost. To overcome these problems efficient methodologies for the high speed design of high-resolution DACs are considered. Behavioral modeling is necessary for the design of complex mixed-mode systems like current-steering DACs. Most of the models constructed (mathematical or circuit based) can not give a complete view of the system's behavior. For this reason, models that speed up the design and reflect accurately the behavior of the system prior to transistor level implementation are developed. The use of DAC modeling tool is helpful to obtain converters having the best performance in terms of speed and accuracy. Through these models (SPICE, Simulink etc. based models), the mixed signal designs even with large complexity can be easily evaluated. To conclude, the efficiency of the applied methodology and the accuracy of the behavioral model are validated through the implementation of a 12-bit hybrid current-steering based DAC in a relatively cheap 0.35µm CMOS process technology. The proposed hybrid DAC consists of four 3-bit parallel matched current-steering subDACs and resistive networks that properly weight the current output of each subDAC to obtain the overall voltage-mode output of the 12-bit hybrid DAC. The improvements in the building blocks and the different approaches used are reflected in the respective parts of the layout of the implemented DAC. Post-layout simulations are obtained using CADENCE Custom IC Design Tools and the performance characteristics of the DAC are investigated. The performance of the implemented DAC is compared with recently introduced DACs designed for different applications, through Figure of Merit (FoM). The architecture and design methodology used for the implementation of the DAC offer advantages like design speed up and a small active area. The performance of the hybrid DAC is validated through static and dynamic performance metrics. All simulations are performed with a 3.3V power supply. Simulations indicate that the DAC has an accuracy of 12-bit and a SFDR higher than 66 dB in whole Nyquist frequency band. The simulated INL is better than 1LSB, while simulated DNL is better than 0.25LSB. At an update rate of 200MSample/s the SFDR for signals up to 1MHz is higher than 70 dB. Similarly at an update rate of 100MS/s the SFDR is higher than 65 dB for signals up to 5 MHz. Even for update rates like 500MSample/s or 1GSample/s the SFDR is higher than 60dB for sinusoidal input signals up to 1MHz. The FoM of the implemented hybrid DAC is better than recently presented DACs with different resolutions and implemented using various process technologies. The proposed hybrid DAC supporting high update rates with good dynamic performance can be used as an alternative in various applications in industry including video, digital TV, cable modems etc. Keywords: Digital-to-analog converter, current-steering, behavioral model, hybrid DAC

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